Hitherto, the two-picture television receiver has been realized in various circuit types. The interlace control circuit is one of the arts necessary for realizing it. That is, in television broad-cast images, one image consists of one frame which is a combination of a first field and a second field; and in order to display two different images (frequencies and phases of their synchronization signals are different each other) on the same picture, it is necessary to make an agreement in field relation between these two. It is the interlace controlling circuit which realizes this.
First, elucidation is made on the interlace controlling circuit of a conventional two-picture television receiver. FIG. 1 is a schematic view of the two-picture television receiver. In the figure, numeral 31 is a televisions receiver, numeral 32 is a main-picture, numeral 33 is a sub-picture which is compressed and synthesized in one part of the main-picture 32.
FIG. 2 is a block diagram of the conventional two-picture television receiver. In the figure, numeral 41 is a cathode-ray tube (hereafter is abbreviated as CRT), numeral 42 is an input terminal whereto an image signal for the main-picture is applied to, and numeral 43 is an input terminal whereto an image signal for the sub-picture is applied. For instance, in a television receiver having two tuners, an image signal made by detecting output signal of the one tuner is applied to the one input terminal 42, an image signal made by detecting and processing output signal of the other signal is applied to the other input terminal 43. And, in a television receiver having one tuner and an input terminal, whereto an image signal output from external apparatus, for instance, video tape recorder or video disc player and so on is impressed, the one image signal is that from the tuner and the other one is from the above-mentioned external apparatus.
Numeral 44 is a circuit part for processing the image signal of the main-picture, numeral 45 is a circuit part for processing image signal of the sub-picture, numeral 46 is an output line of the main-picture processing circuit part 44, numeral 47 is an output line of the sub-picture operation circuit part 45, numeral 48 is a two-input-one-output switch, and numeral 49 is an output line for a signal to deflect CRT 41.
Hereafter, operation of the above-mentioned constitution is elucidated. When the switch 48 is connected to the terminal A, the image signal for the main-picture is conveyed to the CRT 41. When the switch 48 is connected to the terminal B, the image signal for the sub-picture is conveyed to the CRT 41. That is, the switch 48 is connected to the terminal B only when the CRT 41 is scanning by the deflection signal at the part of the sub-picture 33 of FIG. 1. In the sub-picture processing circuit part 45, mainly the following two processings are carried out against the sub-picture image signal inputted from the input terminal 43.
(1) To synchronize with deflection signal of the CRT 41.
(2) To compress the image into the size of the sub-picture 33.
For this purpose, a memory becomes necessary for the sub-picture processing circuit 45. There is prior art, for instance, disclosed in the Gazette of Japanese unexamined published patent application No. Sho 54-156420, which realizes such function by a circuit including two field memory parts.
Hereafter, the above-mentioned conventional sub-picture processing circuit part 45 is explained with reference to FIG. 3. In the drawing, numeral 43 is the input terminal of the image signal for the sub-picture, numeral 47a is the output terminal of the image signal of the sub-picture processing part 45, and numeral 49a is an input terminal of the image signal of the main-picture. Numeral 51 is a field polarity detection part of the sub-picture, numeral 52 is a detection part of the main-picture field polarity, numerals 53 and 54 are memories having a capacity of storing image signals of one field of the sub-picture 33; and therein the numeral 53 is named A-field memory and the numeral 54 is named B-field memory. Numeral 55 is a circuit part for separating synchronization signal from the sub-picture image signal, numeral 56 is an interlace control circuit part, numerals 57 and 58 are switches and numeral 59 is a memory control part.
Next, operation of the sub-picture processing circuit part 45 of the conventional two-picture television receiver is elucidated hereafter. In the field polarity detection parts 51 and 52, field polarities are detected by detecting relations between horizontal synchronization signals and vertical synchronization signals of respective input signals. The output signal of the field polarity detection part 51 of the sub-picture controls the switch 57, and determines in which field memory the sub-picture image signal is to be written. Here, let us provide that the writing is made in the A-field memory 53 when the field of the sub-picture is the first field, and writing is made in the B-field memory 54 when the case is the second field. Readings of the field memories 53 and 54 are fundamentally preferable to be carried out from the A-field memory 53 when the main-picture is the first field, and from the B-field memory 54 when it is the second field.
However, in the two-picture constitution as of FIG. 1, the following problem takes place. That is, in order to compress the size in vertical direction of the sub-picture 33 to 1/N in comparison with the main-picture 32, memory reading-out speed in vertical direction corresponding to the memory writing-in speed must be made N times. That is, in case the switches 57 and 58 are connected to the same field memory, there may take place a case that a vertical direction writing-in is outrun by the vertical direction reading-out. In this case, prior to the outrunning, for instance, newer information of time is displayed in the upper half part of the sub-picture 33, and an older information is displayed on the picture in the lower half part which is the case of after the outrunning, and it make unnatural image in case of the fast moving images.
Therefore, in this conventional example, by means of the interlace control circuit 56, the switch 58 is controlled so that the reading is made from the field memory which does not make the above-mentioned outrunning. In this case, when the A field memory 53 which stores the first field of the sub-picture 33 is read-out in the second field of the main picture 32, the interlace relation becomes abnormal when it is left alone, and therefore a reading of the A-field direction is delayed through the memory control part 59 for one horizontal period.
Hereupon, image source to be inputted as the sub-picture becomes in many varieties recently, and among these, abnormal image signals which are out of the standard of television signal increases. Here, that which becomes a problem is a television signal of non-interlace television. This appears in a personal computer or image at skip play-back of a video tape recorder, and is an image signal having no field polarity. In such case, in the conventional example, the image signal is written in one of the field memories only, since field polarity detection output signal of the sub-picture is fixed. However, since the reading is made alternately from both field memories in the reading, the display becomes in such a state that, on a still-picture which is read-out from the one field memory, a moving-picture which is read-out of the other field memory is superposed, thereby making the image very much unpleasant.